REPLICA-1 PLUS and L-STAR PLUS Expansion Port Help Needed

I don't have any Replica-1 Plus or L-Star Plus (I only have Apple-1 clones and Apple II, real or clones) so I can't give you advice on the specifics of the Replica-1 Plus or L-Star Plus.

But in general, for 6502 systems, your best approach is to use "family" I/O port ICs such as the 6520 ("PIA") or 6522 ("VIA"), as these were specifically designed for the 6502 bus timing. You need no extra components other than some "chip select" signal from an address decoder. Apple-1 has a 74154 address decoder on board, and Apple II uses 74LS138 for the same purpose.

Maybe the Replica-1 Plus or L-Star Plus  also have some spare address decoder outputs, I don't know.

Other than that, hooking up the 6520 or 6522 is trivial, just follow the pattern seen in the Apple-1 manual. You need to connect the data bus, the chip selects, a few lower address lines, and the VCC/GND power supply. The VIA also needs the PHI2 clock.

Then hook up some LEDs (with current limiting resistors) to the I/O ports and start hacking with PEEKS and POKEs in BASIC to configure the 6520/6522 properly (see their datasheets) and try make a "running light" demo.

Then you are there.

As a general rule, avoid "modern" incarnations like the CMOS parts (65C22). Avoid CMOS ICs in +5V TTL systems unless you know exactly what you are doing. Use humble, obsolete, vintage NMOS (6520, 6522) parts and 74LSxxx TTL. You can get 6522 from Surplus Sales of Nebraska and you can get 6520 from Anchor Electronics in Santa Clara. Both have all the TTLs you will ever need in stock.

Do not buy any ICs from China - risk of getting counterfeits is too high. The "6502" they sell on Alibaba mostly are re-stamped CMOS parts which won't work properly in a socket meant for a NMOS 6502.

Modern CMOS is not suited for hobbyists using point-to-point wiring. They switch too fast and cause ringing. Avoid.

- Uncle Bernie

The Replica1 plus has a 74LS138 and 74LS00 on board and a 6821 PIA. I've also used the P-LAB SD card which has it's own VIA on the Replica 1 Plus.

UB, out of sheer curiosity, what are your thoughts on using 74S instead of 74LS series?

In post #3,  skate323k137 asked:

"UB, out of sheer curiosity, what are your thoughts on using 74S instead of 74LS series ?"

Uncle Bernie answers:

First, use Schottky TTL (74Sxxx) only if you need the speed. As long as your wires out of Schottky outputs are no longer than 11", it can be used without inviting all the issues with high speed. If the wires (or PCB traces) are longer, you need at least some form of transmission line effect mitgation. Sometimes a series resistor of 39 Ohms (or so) at the 74Sxxx output can make a signal work that otherwise would ring too badly, despite RF guys would laugh at this crude hack.

The most easy high speed logic to work with is ECL 100k. You do need full impedance controlled wiring, for this there exists twisted pair wire wrap wire. But ECL "steers" a constant current from one branch of the circuit to the other, so there is not much disturbance on the power and ground rails. You can also build smaller ECL circuit using semirigid coax wiring. This is when electronics turn into plumbing.

The problem with CMOS is twofold. With shrinking channel length, CMOS transistors switch faster and faster. Which makes fast signal edges - and there you start inviting the transmission line effects. But the worst problem with CMOS is when static complementary PMOS/NMOS logic is implemented in the traditional way. There is an input voltage range in which both the PMOS and the NMOS branches of a gate conduct, and this makes a fairly low ohmic short circuit between the power rails. The current spike there cannot be sourced over any inductors (such as bond wires or longer metal runs on the IC), so the power supply voltage on the chip collapses locally. It may get so bad that flipflops change state erratically.

With HC and HCT logic families you get the same effect on the board level (because power traces are long enough to be nasty inductors for the di/dt current spikes). ACT and AHCT is even faster and worse. Now, some PLDs and CPLDs did use more advanced CMOS processes which were even faster and then when you clock a bank of macrocells, the whole bank generates such a current spike that some flipflops lose their state, rendering this PLD/CPLD useless.

These effects can be mitigated by circuit tricks in the IC itself, such as sloped controlled output drivers, or by careful design of the on PCB power supply grid using multilayer PCBs and lots of small, low inductance SMD capacitors as power supply bypass to a ground plane. Now, possible resonant frequencies in the 100's of MHz range need to be carefully assessed, or you will get a system which crashes while you sweep the master clock frequency to the critical regions where parasitic resonance on the power grid occurs.

All these effects have plagued the industry since the mid 1980s (when CMOS got fast enough to cause this sort of trouble) and they never have been solved, because it's laws of physics we can't void. Professional digital designers have learned to design around these pitfalls but for the typical hobbyist who neither has the professional background nor the expensive high speed instrumentation in his hobby lab my golden rule applies: stay away from CMOS, and stay away from fast logic families in general unless absolutely needed. Which I don't see a need for in any Apple-1 and Apple II environment.

- Uncle Bernie

P.S.: Oh, and I have lost many MONTHS of my precious and irreplaceable RQLT dealing with such high speed logic ills. I had to scrap whole hobby projects of mine because I had used CPLDs which don't work even if in a perfect environment (the manufacturer later first added fine print like "don't switch more than X flipflops per bank at the same time and later they were bought and the buyer then discontinued this CPLD family because they could not dial down their CMOS processes to be slow enough to make these things work). In my own CMOS IC designs I used a lot of tricks to mitigate these problems, and if need be, I even used CML logic to run stuff at 3 GHz clock speeds without squashing all the analog / mixed signal and RF circuits nearby on the same chip. - Uncle Bernie